Solid-State Transformer (SST) Design: Core Challenges and Key Points Analysis

The Solid-State Transformer (SST), as a power electronic conversion device designed to replace traditional line-frequency transformers, employs a 'power electronic conversion + medium-frequency transformer' structure. It offers significant advantages in efficiency, power density, and control flexibility, but its design difficulty increases substantially accordingly. This article systematically analyzes its core design challenges and key technical points based on the latest industry practices in 2025.

1. SST Core Topology and Design Objectives

A typical SST adopts a three-stage power conversion structure:

• Input Stage (AC/DC): Responsible for rectifying medium-voltage AC (e.g., 10 kV) into a stable DC bus voltage (e.g., 800 V). Mainstream topologies are three-phase VIENNA rectifiers or cascaded H-bridges, requiring the use of 10 kV SiC MOSFETs or 3.3 kV IGBT series connection schemes. The design targets for this stage are efficiency above 99% and input current total harmonic distortion (THD) below 5%.
  
• Isolation Stage (DC/DC): Provides electrical isolation and voltage matching. Typically, Dual Active Bridge (DAB) or DCX topologies are used, with switching frequencies in the range of 20–100 kHz, relying on the Medium Frequency Transformer (MFT). This stage is the 'heart' of the SST, with a target efficiency exceeding 98%.
  
• Output Stage (DC/AC or DC): Converts DC to 50 Hz/400 Hz AC or maintains DC output according to load requirements. It must also possess seamless transition capability between grid-connected and off-grid modes.
  

2. Analysis of Core Design Challenges

The design challenges of SST mainly focus on the contradictory unification of high frequency, high voltage, and high power density, manifesting in six industry-recognized key difficulties.

1. Medium-Voltage Insulation Requirements 'Do Not Decrease with Frequency'
High-frequency operation does not reduce insulation requirements. The MFT must fully meet line-frequency 42 kV/1 min withstand voltage and 75 kV lightning impulse insulation level (BIL). According to the IEC 62477-2 standard, the minimum creepage distance for the 10 kV voltage level needs to be ≥32 mm, and the clearance ≥16 mm. These safety distance requirements occupy about 40% of the transformer's volume. More critically, the high-frequency electric field concentration effect can reduce the partial discharge (PD) inception voltage by approximately 30%, especially at the epoxy resin-air interface. A composite insulation structure combining shielding layers with Vacuum Pressure Impregnation (VPI) must be employed for suppression.

2. Multidimensional Superimposition of High-Frequency Losses
Within the 20–100 kHz range, loss mechanisms are complex and severe:

• Core Loss: The typical core loss of nanocrystalline ribbon (e.g., 26 µm thickness) can reach 25 W/kg under conditions of 25 kHz, 0.4 T, with internal eddy current losses in large cross-section cores potentially increasing by an additional 40%.
  
• Winding Loss: Skin effect and proximity effect dominate at high frequencies. For example, the AC resistance of foil windings can be more than 3 times the DC resistance at 50 kHz.
  
• Switching Loss: In soft-switching topologies like DAB, if the Zero Voltage Switching (ZVS) condition is lost for merely 200 ns, the power semiconductors fall into hard switching, potentially doubling their switching loss instantly, posing a fatal threat to the devices.
  

3. Precision of Leakage Inductance as a Key Control Parameter
In the DAB topology, the transformer leakage inductance (Lσ) is a key control parameter for power transfer. The power transfer formula is:
P = (n·V₁·V₂)/(8·f·Lσ) · φ(1 − φ/π)
where φ is the phase-shift angle. The industry requires the leakage inductance value to be controlled within a ±5% tolerance range. Winding one turn more or less can cause the parameter to exceed specifications, leading to system instability. Therefore, using a shell-type (E-core) magnetic core structure combined with segmented interleaved winding methods has become the mainstream solution in 2025 for precise leakage inductance control.

4. Lack of Technical Standards for 10 kV Hot-Swap
For application scenarios like data centers that pursue extremely high availability, customers require the ability to replace faulty modules online on the medium-voltage side (10 kV). However, there is currently a lack of mature commercial 10 kV hot-swap connector solutions and related national standards in the market, necessitating complete system shutdown for maintenance, which is an obstacle to large-scale application.

5. Stringent Requirements for Modular Series Voltage Balancing Accuracy
To handle high input voltage, an Input-Series Output-Parallel (ISOP) modular architecture is often adopted. If 10 modules are connected in series, a voltage balancing accuracy deviation of just 1% can cause the leading module to withstand over 200 V of extra voltage, easily leading to device overvoltage breakdown. Achieving voltage balancing requires high-speed control, typically demanding a voltage balancing loop bandwidth of 1 kHz, and inter-module synchronization via optical fiber with a delay of less than 50 ns.

6. The 'Three Major Cost Barriers'

• Magnetic Material Cost: High-performance nanocrystalline cores cost about 180 RMB/kg, which is 15 times the price of traditional silicon steel sheets (about 12 RMB/kg).
  
• Semiconductor Device Cost: The unit price of 10 kV SiC MOSFETs is high (about 1340 RMB/piece). A single-phase full bridge requires 4 pieces, and multiple modules need to be paralleled to meet power requirements.
  
• Insulation and Heat Dissipation Cost: The thermal conductivity of conventional potting epoxy resin is only about 0.2 W/(m·K). To improve heat dissipation, it is necessary to add high thermal conductivity fillers like Aluminum Nitride (AlN) and design micro-channels, increasing costs by another approximately 25%.
  

3. Key Technical Points and Design Guidelines

To address the above challenges, the following validated design key points have been established.

1. Optimized Design of Medium Frequency Transformer (MFT)

• Core Material Selection: Prefer 26 µm nanocrystalline ribbon for operating frequencies ≥15 kHz; consider 30 µm amorphous material for<15 kHz, reducing cost by about 30%.
  
• Winding and Structure: Use segmented interleaved foil winding, which can reduce proximity effect losses by up to 40%; selecting a shell-type (E-core) structure facilitates mechanical fixation and leakage inductance control.
  
• Insulation Treatment: Use a combination of high-temperature Nomex paper and Polyimide (PI) film, controlling the interlayer field strength to<3 kV/mm. After overall Vacuum Pressure Impregnation (VPI) treatment, the creepage distance can be reduced by about 20% while ensuring insulation.
  
• Integrated Cooling: Use copper foil windings with built-in micro-channels to achieve direct contact between the windings and the coolant, reducing thermal resistance to below 0.08 K/W, thereby decreasing volume by about 30%.
  

2. Power Semiconductors and Drive Protection

• Device Selection and Operating Mode: Must select 10 kV SiC MOSFET modules and ensure ZVS across the full load range through precise phase-shift control. Even if a small amount of circulating current needs to be injected at light load (sacrificing about 2% of light-load efficiency), hard switching must be avoided.
  
• Low-Inductance Packaging: Must use laminated busbars (e.g., 2 mm copper layer + 0.5 mm insulation) to control power loop stray inductance below 5 nH. When the turn-off current change rate (dI/dt) reaches 1000 A/µs, the voltage spike can be suppressed within 500 V.
  
• High-Speed Drive and Protection: The drive circuit needs to have a peak drive capability of ±6.5 A and a turn-off bias of -4 V. It must integrate short-circuit protection capable of responding within 2 µs and employ a soft-turn-off strategy with a slope of about 20 A/µs.
  

3. System-Level Reliability and Redundancy

• Architectural Redundancy: Achieve N+1 redundancy for power modules, use dual redundant 24V hot-swappable inputs for control power, and employ an optical fiber ring network for communication. Ensure faulty modules can be reliably bypassed within 10 ms.
  

4. Industry Status and Outlook

 Industry consensus is that the 800 V DC bus-based data center power architecture is expected to move towards large-scale adoption by 2027, but this is predicated on completely resolving the 10 kV hot-swap technology and long-term reliability verification issues.

SST design is essentially about finding the optimal solution under the triple constraints of high-frequency losses, insulation safety distances, and heat dissipation capability. The feasible path for 2025 is clear: 'Nanocrystalline shell-type core + segmented interleaved winding + composite insulation with micro-channel cooling.' Following this route for selection and design, an engineering prototype can be completed in approximately 4 weeks, achieving advanced laboratory indicators of 98.3% efficiency and 1.25 kW/L power density, paving the way for the final commercialization of SST. In the future, reducing MFT cost (currently accounting for about 18% of SST BOM cost) and perfecting medium-voltage hot-swap standards will be the focus of industrial research and development.