10kV SST high-frequency transformer design: start from the system boundary, not the core

Designing a 10kV-class solid-state-transformer (SST) high-frequency transformer, two pitfalls are common: starting the design from a core part number, and treating winding optimization as 'make the leakage small.' A design that actually lands starts from the system boundary — freeze the waveform and insulation stress first, then fix volt-second, core and turns, compare winding structures, and keep back-fitting with EM, thermal, PD and prototype tests.

1. Define the inputs first: the starting point is not core selection

Before opening the core catalogue, write the design inputs as a boundary table: primary/secondary voltage range, actual bridge-arm waveform, minimum switching frequency, maximum effective duty cycle, power and current spectrum, cooling condition, altitude and pollution degree, and the longest one-way volt-second that can appear during start-up, shut-down or fault cut-off. The easiest to miss is the abnormal condition — DAB, PSFB and LLC may be perfectly symmetric at the rated point, but dead-time, soft-start, control saturation and protection delay all change the volt-second applied to the winding; checking only the rated point does not prove there is no asymmetry before start-up or fault.

Also clarify what '10kV' actually means: system rated voltage, highest equipment voltage, isolated-stage port voltage, or test withstand level. The four definitions imply different insulation-coordination boundaries and must not be mixed.

2. Derive turns from volt-second, then discuss material and volume

Within any voltage interval, flux-density change follows the volt-second relation: an ideal symmetric square wave reduces to the familiar turns formula; for an isolation stage with dead-time, three-level intervals or resonant waveforms, integrate the actual winding voltage directly. The design table must at least check max bus with min frequency, rated power, the largest asymmetric soft-start pulse width, and the longest one-way volt-second before protection trips.

Allowed flux density is not the saturation flux from the datasheet — temperature, DC bias, assembly air-gap, clamping stress, control asymmetry and batch scatter all need margin. Nanocrystalline, amorphous and ferrite should not be split by a fixed frequency line either; the meaningful comparison is, under the same voltage waveform, the same temperature rise target and the same insulation window, compute core loss, required cross-section, window fill and manufacturing cost. The material label only helps screening, not duty-cycle calculation.

On frequency vs core (core vendor datasheets: Hitachi Metals FINEMET, Ferroxcube 3C95, TDK PC200; Cu conductor at 100℃): 20kHz uses nanocrystalline (Bs≈1.2T), 50kHz still nanocrystalline, 100kHz moves to 3C95 ferrite (Bs≈0.4T), 200kHz needs PC200-class (Bs≈0.32T, with thin core limbs + interleaving to lower ΔB). Skin depth, conductor spec, max interleave layers and module power per frequency are in the table and figure below.

3. Compare winding structures on four quantities at once

Concentric, fully interleaved, partially interleaved and segmental-pancake windings must be compared on at least four metrics: total series inductance, primary–secondary equivalent capacitance, AC copper loss and maximum local field. Chasing leakage alone often grows another term.

• Concentric: simple structure, clear insulation boundary, easy process consistency; the cost is a longer leakage path. Fits when insulation and manufacturing stability come first, or the system itself needs some series inductance.
• Fully interleaved: shortens the leakage path but increases the adjacent area of HV and LV windings, raising coupling capacitance and common-mode displacement current; splitting the HV winding into more sections also makes inter-/intra-layer insulation, leads and end-field more complex.
• Partially interleaved: through segment count, adjacent area and inter-segment distance, trades between leakage, capacitance, copper loss and insulation — the more practical degree of freedom.
• Segmental pancake: good for axial potential control and leaves channels for cooling and insulation; but inter-segment connections, end proximity fields and tooling tolerance must be modeled together — more segments are not automatically better.

DAB's goal is not 'zero leakage.' With turns ratio n=Np/Ns referred to primary, the total series inductance includes not only transformer leakage but also external inductors and busbar parasitics; power P = n·V₁·V₂ / (2πf·Lσ) · φ(1−φ/π), and transfer and the ZVS region depend on that total. DAB leakage must be designed precisely; a typical process-control target is ±5% order of magnitude — one turn more or less can exceed spec, causing phase-shift loss of control and ZVS disappearance (Univ. of South Carolina leakage-optimization study shows model vs measured within ~5%; IEEE JESTPE 2024 10kV SiC DAB also stresses that leakage integration and tolerance affect ZVS, and once ZVS is lost switching loss rises sharply). Integrating all series inductance into the transformer saves components, but winding size and process tolerance become the dispersion of power and soft switching directly.

High-frequency copper loss is not just I²R_DC. Foil thickness, layer count, end leakage field and current harmonics together set skin and proximity loss; foil is not inherently better than Litz, and Litz only helps when strand diameter, twist pitch, parallel current sharing and termination are right. The Dowell model suits early screening, but MV windings often show clear 2D/3D field effects at ends, segment gaps and shield edges — finally correct the AC resistance from field simulation against impedance test, calorimetry or temperature rise.

4. Insulation must face real PWM, not just power-frequency withstand

A 10kV-class HF transformer must distinguish at least five field regions: turn-to-turn, layer-to-layer, winding-to-winding, winding-to-core-or-shield, and end leads. Low average field does not mean safe — conductor edges, shield terminations, triple points, voids and material interfaces are where PD usually starts. A 10kV system per IEC 60076-11 still requires 75kV BIL (12kV-class lightning impulse; per IEEE C57.12.00 15kV class or engineering margin 95kV BIL is commonly adopted), winding spacing ≥16mm, resin/insulation thickness ≥3mm; per IEC 62477-2 the creepage at 10kV is ≥32mm and clearance ≥16mm. Stepped insulation plus field-shielding rings can pull peak field from 3.5kV/mm to 2.2kV/mm and keep apparent discharge below 5pC.

IEC 60076-11:2018 applies to dry-type power transformers with highest equipment voltage up to 72.5kV and at least one winding above 1.1kV, giving a framework for environmental, thermal and dielectric tests; IEC 62477-2:2018 covers power-electronic conversion systems from 1kV AC / 1.5kV DC up to 36kV AC / 54kV DC. But neither replaces verification against actual high-dv/dt repetitive pulses — PD under PWM must record rise time, repetition frequency, pulse width, background noise, calibration method, PDIV/PDEV criteria and preconditioning, or tests are not comparable.

Potting is not simply 'fill the gaps': resin viscosity, vacuum profile, cure exotherm, CTE and interfacial adhesion all affect voids, cracks and delamination after thermal cycling.

5. Thermal design watches the hottest spot, not 'average rise'

Core loss depends on frequency, flux swing, temperature and waveform; the classic Steinmetz formula fits only near its calibration, so non-sinusoidal excitation needs a matched improved model, back-fitted with prototype rise or calorimetry. Winding loss applies each harmonic current to a frequency-dependent AC resistance; shields, clamps and nearby metal also add eddy-current loss that, if ignored in the model, lets a normal surface rise hide an internal hot spot.

MW-class SST power density has reached 223 kW/m² (IEEE ECCE 2024, measured on a 2MW 10kV SST); the HF transformer is a major loss and volume source with high internal heat flux. Thermal design follows the IEC 60076-11 dry-type winding rise limit (class-F 100 K), and high-reliability designs keep hot-spot rise lower (e.g.,<40 K); nanocrystalline cores allow 120℃, potting silicone tops 180℃. The thermal network should at least cover core-to-ambient, winding-to-potting, potting-to-housing, and hot-spot-to-sensor. Thermocouples tend to underestimate internal hot spots and IR thermography suffers from emissivity and occlusion — safer to import the loss distribution into a thermal model and close the energy balance with multi-point temperature, winding-resistance method and coolant rise.

6. Before the full unit, build three low-cost test coupons

• Insulation-interface coupon: reproduce the triple point with real copper edge, film, tape and potting; check PDIV/PDEV under power-frequency, DC and repetitive pulses, and watch thermal cycling.
• Winding-window coupon: validate target conductor, inter-layer insulation, winding tension, min radius, inter-segment connection and lead forming — expose 'drawable but not windable' early.
• Thermal-path coupon: build the actual winding–potting–housing material and thickness; measure equivalent thermal resistance, interface integrity and crack/delamination risk after thermal cycling.

Coupons do not replace the unit, but they separate material, process and structure problems. Jumping straight from a 2D drawing to a potted prototype, a single PD failure usually leaves only the vague conclusion 'maybe there was a void.'

7. Close the simulation–prototype–test loop

A reliable flow is not computed once but continuously back-fitted: voltage waveform sets volt-second and insulation stress; winding structure sets leakage, capacitance and copper loss; these enter control, common-mode and thermal models; PD and temperature results then bound flux, power and structure. After the first article, split parameters into two groups — turns, conductor size, layer gap, material batch and cooling flow are directly measurable, freeze them; leakage, AC resistance, thermal resistance and equivalent parasitics must be identified, then back-fitted by test.

If leakage is high, check winding spacing, interleave position and leads; if AC resistance is high, check end proximity field, foil thickness and parallel-branch current sharing; if PDIV is low, locate ends, voids and triple points first — do not simply thicken all insulation at once. After back-fitting, keep one set of frequency / temperature / load conditions unused in the fit for cross-validation; a model that matches only at the rated point cannot support the next revision.

8. Acceptance values must carry test conditions

'Good efficiency' is not enough; what is deliverable is a reproducible parameter window with tolerances: leakage notes referred side, test frequency, how the other side is shorted, test current and fixture compensation; capacitance notes port connection, shield state, frequency range and equivalent model; PD notes applied waveform, background noise, calibration, PDIV/PDEV criteria and preconditioning; temperature rise notes coolant inlet temperature, flow, thermal-steady criterion and hot-spot method; loss and efficiency note waveform, power, temperature, instrument bandwidth and uncertainty; process records winding tension, insulation overlap, vacuum and cure profile, and material batch. Only when these can be reproduced by the next article, a second supplier and the system control model is the design truly closed.

Closing

A 10kV SST HF transformer is not four independent problems — core, turns, winding and insulation — but a set of interlocking constraints: volt-second sets flux, winding changes leakage, capacitance and copper loss, insulation and thermal design set the usable window, and manufacturing tolerance decides whether those parameters land stably. What is hardest for you to coordinate right now — target leakage vs parasitic capacitance, end-field vs window utilization, or potting process vs internal hot spot?